The invention relates to a phase-locked loop (PLL) which multiplies an input signal frequency to a given value and delivers it as an output, and in particular, to a PLL in which the output follows the input signal frequency over an extensive frequency range.
A PLL frequency synthesizer circuit is used in a tuning circuit of a mobile communication equipment such as a digital cordless telephone or a portable telephone. The PLL frequency synthesizer circuit is an oscillator which can oscillate at a number of exact frequencies which are spaced apart at an equal interval, and is indispensable as a local oscillator in a mobile communication equipment.
A PLL of the kind described is disclosed, for example, in Japanese Laid-Open Patent Application No. 344,712/92 which discloses a PLL synchronization signal generator. This arrangement aims at reliably producing an output signal which is synchronized with an input signal whose frequency varies over an extensive range, and includes a plurality of combinations of low-pass filters (LPFs), each having a given frequency bandwidth, and associated voltage-controlled oscillators (VCOs), as well as a frequency measuring circuit which determines the frequency of an input signal. The result of the measurement by the frequency measuring circuit is used to operate a switch to select one of the outputs of the combinations of the LPFs and the VCOs.
However, the above-described PLL, synchronization signal generator requires a plurality of combinations of the LPFs and the VCOs, and the frequency measuring circuit, and is therefore undesirably complex and voluminous.